The present invention relates to a semiconductor device and a manufacturing method thereof, more specifically, a semiconductor device having a plurality of gate electrode structures and a manufacturing method thereof.
In CMOS devices after 45-nm node ones, replacement of a structure having poly-Si as a gate electrode and SiON as a gate insulating film with a gate stack structure having a high-dielectric-constant insulating film (which will hereinafter be called “high-k film”) as the gate insulating film has been started. This replacement occurs because compared with a SiO2 film or the like, a high-k film functions as a thin film during electric operations, though it is physically thick, in other words, it has a small effective thickness so that it can contribute to the control of a gate leakage current.
In such a poly-Si/high-k film structure, however, a fermi level pinning phenomenon causes an increase in threshold voltage (Vth) at the time of device operation. This problem is particularly prominent in the threshold voltage of pMOSFET.
Injection of fluorine (F) ion into a Si substrate prior to the formation of a gate insulating film is proposed as a measure for reducing the threshold voltage (Vth) of pMOSFET (refer to M. Inoue, et al., IDEM Tech. Dig., p. 425 (2005)). Injection of a large amount of F ion into the Si substrate is however necessary in order to achieve desired device characteristics. Injection of a large amount of F ion into the Si substrate deteriorates device characteristics because of damage caused by injection.
As another measure for reducing the threshold voltage (Vth) of nMOSFET, injection of nitrogen (N2) ion into the Si substrate prior to the formation of the gate insulating film is proposed. Injection of a large amount of N2 ion into the Si substrate also deteriorates device characteristics because of damage caused by injection.
Since a work function has a direct relation to the threshold voltage (Vth) of FET, use of a metal material having a desired work function for a gate electrode is proposed as a measure for reducing the threshold voltage (Vth). A first advantage of using a metal material for the bottom layer of the gate electrode resides in that since a metal gate electrode, different from a poly-Si gate electrode, does not generate a depletion layer, an increase in the effective thickness of a gate insulating film at the time of device operation due to depletion does not occur, making it possible to realize a high-performance device. A second advantage resides in that difficulty in controlling a threshold voltage due to fermi level pinning can be avoided.
In CMOS devices, use of a metal material having a work function suited for each of pMOSFET and nMOSFET is preferred so that Japanese Patent Laid-Open Nos. 2007-242894, 2007-141889, and 2005-294799 each proposes a method of controlling the material and crystal phase between n/p-MOS in a fully-silicided gate electrode using a Si film as the bottom layer of the gate electrode. Japanese Patent Laid-Open No. 2007-142153 proposes a method of controlling, in a metal gate of n/p-MOS, nitrogen diffusion between a metal film/metal nitride film using metal materials of the same kind, thereby controlling the work function of a metal gate electrode. These proposals however have a problem because they complicate the production flow and make the production process difficult.
In order to avoid such problems, development of a hybrid metal gate CMOS device equipped with pMOSFET having a poly-Si/metal/high-k structure and nMOSFET having a poly-Si/high-k structure is promoted (refer to T. Hayashi, et al., IDEM Tech. Dig., p. 247 (2006)).
Further, formation of respective gate electrodes suited for pMOSFET and nMOSFET complicates the production process so that a method of capping a gate insulating film to form two kinds of gate insulating films is under investigation (refer to, for example, V. Narayanan et al. VLSI Tech. Symp., p. 224 (2006).